1. Field of the Invention
The present invention generally relates to a parallel compression test circuit of a memory device, and more specifically, to a technology of sequentially operating write drivers in a parallel compression test mode to disperse current and reduce noise.
2. Description of the Related Art
FIG. 1 is a block diagram illustrating a conventional parallel compression test circuit of a memory device.
The conventional parallel compression test circuit comprises a memory unit 10, a write driving unit 20, a write driving control unit 30, a global input/output write driving unit 40 and a data input buffer 50.
The memory unit 10 comprises four banks 12 and four bit line sense amplifiers 14. Here, data on local input/output buses LIOT0˜LIOT3 and LIOB0˜LIOB3 are stored in the banks 12 through the bit line sense amplifiers 14.
The write driving unit 20 comprises four write drivers 22 corresponding to each bank 12. Each write driver 22 drives data on corresponding one of global input/output lines GIO0˜GIO15 to transmit the data to the bit line sense amplifiers 14 of the corresponding bank 12.
The write driving control unit 30 generates a write driving control signal WYP to control the driving operation of the write driving unit 20.
The global input/output write driving unit 40 comprises a plurality of global input/output write drivers 42. Each global input/output write driver 42 drives data Din0˜Din15 inputted in response to a test mode signal TPA to transmit the data to the global input/output lines GIO0˜GIO15.
The data input buffer unit 50 comprises a plurality of data input buffers 52 for temporarily storing externally inputted data to output the data to the global input/output write driving unit 40.
FIG. 2 is a circuit diagram illustrating the write driving control unit 30 of FIG. 1.
The write driving control unit 30 comprises a delay unit 32 and inverters IV1˜IV4. The inverters IV1 and IV2 sequentially inverts a column operation pulse signal YP, and the delay unit 32 delays an output signal from the inverter IV2 for a predetermined time T1.
The inverters IV3 and IV4 sequentially inverts an output signal from the delay unit 32 to generate the write driving control signal WYP.
FIG. 3 is a timing diagram illustrating the operation of the parallel compression test circuit of FIG. 1.
In a parallel compression test mode, a write operation is performed only on the data Din˜Din3 corresponding to the number of the banks 12 by the global input/output write driving unit 40.
When the parallel compression test mode signal TPA is enabled, 4–15 of the global input/output write drivers 42 drive the data Din0–Din3 instead of data Din4˜Din15 inputted in a normal mode.
That is, the Din0 is driven by the global input/output write drivers 0, 4, 8, 12, the Din1 is driven by the global input/output write drivers 1, 5, 9, 13, the Din2 is driven by the global input/output write drivers 2, 6, 10, 14, and the Din3 is driven by the global input/output write drivers 3, 7, 11, 15.
The data driven by the global input/output write drivers 42 are inputted in the write drivers 22 comprised in each bank 12 through the global input/output lines GIO0˜GI015.
The write drivers 22 drives data on the global input/output lines GIO0˜GIO15 in response to the write driving control signal WYP outputted from the write driving control unit 30, and transmits the data to the local input/output lines LIOT0˜LIOT3 and LIOB0˜LIOB3. Here, the write drivers 22 are simultaneously driven in response to the same write driving control signal WYP.
In other words, the same write driving control signal WYP is applied to all of the write drivers 22 regardless of the banks 12, so that data of 16 bits in each bank 12, which are totaled to 64 bits, are simultaneously written.
As a result, high peak current and noise can be generated because the write drivers 22 of the four banks 12 are simultaneously operated in the parallel test mode rather than in the normal mode.
Although the example where the data of 64 bits are simultaneously outputted by the four banks 12 is illustrated herein, in case of a DDR2 SDRAM, current consumption more increases because data of 256 bits are simultaneously written, thereby generating noise.